Special Issue 2025

1. Yield Analysis and Modeling:
   Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
2. Testing Techniques:
   Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing.
3. Design For Testability in IC Design:
   FPGA, SoC, NoC, ASIC, low-power design and micro-processors, including RISC-V architectures
4. Error Detection, Correction, and Recovery:
   Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes; space/time redundancy; HW/SW techniques; architectural and system-level techniques.
5. Dependability Analysis and Validation:
   Fault injection techniques and frameworks; dependability and characterization; cross-layer reliability analysis; dependability analysis for AI and machine learning.
6. Repair, Restructuring and Reconfiguration:
   Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGAs.
7. Defect and Fault Tolerance:
   Reliable circuit synthesis; fault tolerant design; design space exploration for dependable systems.
8. Radiation effects:
   SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening.
9. Aging and Lifetime Reliability:
   Aging characterization and modeling; design and run-time reliability. Variability management and recovery.
10. Dependable Applications and Case Studies:
    Methodologies and case studies: 2.5D/3D ICs, IoT, automotive/railway/avionics/space, autonomous systems, industrial control, fail-safe systems, dependable AI.
11. Emerging Technologies:
    Error management techniques for memristors, spintronics, microfluidics, approximate computing, etc.
12. Design for Security:
    Fault attacks; fault tolerance-based countermeasures; scan-based attacks and countermeasures; hardware trojans; system obfuscation; secure AI. Interactions between VLSI test, trust, and reliability.

Extended journal versions of papers from the 38th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems 2025 are welcome. Extended papers must contain at least 30% of new material different from the original work published in the conference proceedings preferably with a reformulated text of the unmodified parts.

Important dates

Manuscript submission information

Submission details will be available soon. However, we kindly ask potential authors to preliminarily express their interest by sending an e-mail to the Guest Editors. Please read the Guide for Authors submission instructions.