Special Issue 2024

1. Yield Analysis and Modeling:
   Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
2. Testing Techniques:
   Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.
3. Design for Testability in IC Design:
   FPGA, SoC, NoC, ASIC, low power design and micro-processors, including RISC-V architectures
4. Error Detection, Correction, and Recovery:
   Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques.
5. Dependability Analysis and Validation:
   Fault injection techniques and frameworks; dependability and characterization, cross-layer reliability analysis, dependability analysis for AI and machine learning.
6. Repair, Restructuring and Reconfiguration:
   Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.
7. Defect and Fault Tolerance:
   Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults.
8. Radiation effects:
   SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.
9. Aging and Lifetime Reliability:
   Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.
10. Dependable Applications and Case Studies:
    Methodologies and case studies: 2.5D/3D ICs, IoT, automotive/railway/avionics/space, autonomous systems, industrial control, fail-safe systems, dependable AI.
11. Emerging Technologies:
    Error management techniques for quantum computing, memristors, spintronics, microfluidics, approximate computing, etc.
12. Design for Security:
    Fault attacks, fault tolerancebased countermeasures, scan-based attacks and countermeasures, hardware trojans, system obfuscation and logic locking, secure AI, security vs. reliability, interaction between VLSI test, trust, and reliability.

Extended journal versions of invited papers from the 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems 2024 are welcome. Extended papers must contain at least 30% of new material different from the original work published in the conference proceedings possibly with a reformulated text of the unmodified parts.

Important dates

Manuscript submission information

All manuscripts should be submitted via the Elsevier online system of the journal, available at MICPRO editorial manager. When submitting the paper, please select “VSI: DFTS 2024” as the article type.

Please read the submission instructions: Guide for Authors.