Call for Papers

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DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies, RISC-V architectures and AI-based solutions. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, availability, and security that are affected by defects during manufacturing and by faults during system operation are of interest. Topics include (but are not limited to) the following:

1. 1. Yield Analysis and Modeling
   Advanced yield models, defect/fault analysis, statistical modeling, and critical area analysis.
2. 2. Testing Techniques
   Innovative testing methodologies for digital, analog, and mixed signal circuits, including built-in self-test, delay fault testing, online test and 2.5D/3D circuits.
3. 3. Design For Testability
   DFT for modern ICs, including FPGAs, SoCs, NoCs, GPUs, ASICs, low-power designs, and RISC-V designs.
4. 4. Error Detection, Correction, and Recovery
   Robust error handling strategies, including error-control coding, fault masking, and recovery schemes, using hardware/software techniques and architectural approaches.
5. 5. Dependability Analysis and Validation
   Rigorous evaluation of system dependability, employing fault injection, cross-layer reliability analysis, and AI/ML-based methods.
6. 6. Repair, Restructuring and Reconfiguration
   Dynamic adaptation techniques for fault tolerance and resilience, including self-healing reconfigurable circuits, and on-line repair.
7. 7. Defect and Fault Tolerance
   Design of reliable systems in the presence of defects and faults, design space exploration for dependable systems, in critical applications and addressing transient/soft faults.
8. 8. Aging and Radiation effects
   Radiation effects, radiation-induced errors in nano-technologies, modeling radiation environments, development of novel radiation test and simulation techniques and developing radiation hardened designs.
9. 9. Aging and Lifetime Reliability
   Understanding aging mechanisms, designing for long-term reliability, and managing thermal and variability challenges.
10. 10. Emerging Technologies
    Error management strategies for quantum computing, memristive devices, spintronics, microfluidics, and approximate computing.
11. 11. RISC-V
    Use of open ISAs in dependable and security applications.
12. 12. Design for Security
    Protecting ICs against fault attacks, hardware trojans, and other security threats, the interplay between security, reliability, and trust.
13. 13. Dependable Applications and Case Studies
    Real world applications of dependability techniques in 2.5D/3D ICs, IoT, automotive, aerospace, autonomous systems, and AI systems.
14. 14. Sustainability and Green EEE
    Highlight the need for energy-efficient and environmentally friendly EEE designs, including low-power design techniques and green manufacturing processes.

Paper Submission: Authors are invited to submit original and unpublished contributions in the areas described above. Authors must first submit a one paragraph abstract, followed by the final paper for review. Submitted papers should be no longer than 6 pages and adhere to the IEEE conference template, 2-columns style (available on conference web site). Papers can be accepted as regular papers or short papers. Both types of paper will be included in the IEEE proceedings. The page limit for proceedings is 6 pages for regular papers and 4 pages for short papers. Authors of a 6 page submission accepted as a short paper must reduce it to 4 pages, for publication. Full paper versions of relevant work presented, or under submission, for the RISC-V Summit are welcome. Please refer to the symposium web page for updated information.

Paper Publication: Only original, unpublished work will be accepted, for oral presentation at the symposium. Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library

Author Registration: Every accepted paper MUST have at least one full paid registration by the time the camera-ready paper is submitted for inclusion in the proceedings, and one of the authors MUST attend the Symposium and present the paper.

Best Paper Award: The committee will select a best paper award and best student paper awards which will be attributed at the conference.

Journal Special Issue associated with the conference: Authors of accepted papers at DFTS will be invited to submit an extended version of the work to a special issue of an area journal dedicated to the conference edition.