This is a preliminary program, and details may change.
08:30
09:00
10:00
11:00
12:00
13:00
14:00
15:00
16:00
17:00
18:00
21:00
08:30
09:00
Opening
09:30
09:30 -
10:30
Keynote
Keynote by Luca Benini
10:30
Coffee Break
10:50
Session 1: Dependable AI and Machine Learning
10:50 -
12:00
Regular
Session
10:50
On the Efficacy of Vector Retrieval System under Hardware Faults
Vishal Thomas, Ussama Zahid, Giulio Gambardella, Haralampos G Stratigopoulos and Brian Clerkin
11:10
FIRM: Fault-Tolerant Quantized Neural Networks with Data Representation-Aware Adaptive Margin-Based Cross-Entropy Loss
Maryam Eslami, Mikail Yayla, Salim Ullah and Akash Kumar
11:30
On the Dependable Operation of Key-Value Caches in Large Language Models (LLMs)
Zhen Gao, Jie Deng, Shanshan Liu, Pedro Reviriego, Xiaochen Tang and Lombardi Fabrizio
11:40
Benchmarking Dataset Sampling Techniques for Reliability Analysis of Deep Neural Networks
Nikolaos Zazatis, Alessandro Veronesi, Leticia Maria Bolzani Pohls, Marko Andjelkovic, Christos Sotiriou and Davide Bertozzi
11:50
CheckOne: Lightweight Fault Detection and Mitigation for Vision Transformers
Mohammad Hasan Ahmadilivani, Sven-Markus Loorits and Jaan Raik
12:00
Lunch
13:30
13:30 -
14:30
Keynote
Keynote by Janusz Rajski
14:30
Session 2: Fault Injection, Modeling, and Fault Tolerance
14:30 -
16:00
Regular
Session
14:30
X-Ray Fault Injection Attack on Single Transistor in 22nm Fully-Depleted Silicon On Insulator
Edouard Franco, Laurent Maingault, Stéphanie Anceau, Alejandro Urena-Acuna, Guillaume Hubert, Sophie Bouat and Rémi Tucoulou
14:50
An Iterative Post-Placement Optimisation Flow for Single Event Transient Hardening in VLSI Circuits
Christos Georgakidis, Nikolaos Zazatis, Pavlos Chatzis, Nikolaos Chatzivangelis, Christos P. Sotiriou, Marko Andjelkovic and Milos Krstic
15:10
Assessing Triple Modular Redundancy for Wide-Link, Low-Latency NoC Routers: Reliability and Physical Design Challenges
Chen Wu, Michael Rogenmoser, Luca Benini and Angelo Garofalo
15:30
Error Tolerance of Continuous Simultaneous Localization and Mapping (SLAM) Systems: Analysis, Evaluation and Protection
Xiuyuan Qi, Shanshan Liu, Yongyi Su, Xiaochen Tang, Pedro Reviriego, Zhen Gao and Fabrizio Lombardi
11:50
Complete SEU Vulnerable Register Enumeration using Property Directed Reachability
Félix Ridoux, Antoine Schohn, Souheib Baarir, Jean-Marc Daveau and Philippe Roche
16:00
Coffee Break and Poster Session
16:00 -
17:00
Poster
Session
Designs of Triple-Modular Redundancy (TMR) Schemes for Continuous Data Sets
Salin Junsangsri and Fabrizio Lombardi
Flip-MoE: Characterizing Fault Resilience of Mixture-of-Experts Architectures under Weight-Level Bit Flips
Omkar Shende, Marcello Traiola and Gayathri Ananthanarayanan
Design and Evaluation of a Distributed Voter for Triple Modular Redundancy in Rust
Darío González-Montesoro, Alejandro Serrano-Cases, Rodrigo Possamai-Bastos, Sergio Cuenca-Asensi, Emmanuel Atukpor and Antonio Martínez-Álvarez
Enhancing Long term radiation effect tolerance of 45 nm NAND Flash memories via early annealing
Alessandro Romano, Boubakr Rahmani, Stéphanie Anceau, Remi Granger, Luc Salvo and Jérémy Postel-Pellerin
Proton-Induced Radiation Effects on 28nm Artix-7 RISC-V Microprocessor Design
Marcello Barbirotta, Marco Angioli, Andrea Marcelli, Antonio Mastrandrea, Francesco Menichelli and Mauro Olivieri
Verified DRAM Address Mapping Reverse Engineering with Threshold Sweep
Hewen Zhang and Ian Harris
SAISEI: Streamed Automated IC Test Sequence Execution Interface
Zhenzhe Chen and Takashi Sato
17:00
Session 3: Reliable and Secure RISC-V Systems
17:00 -
18:10
Regular
Session
17:00
Design and Reliability Analysis of a Fault-Tolerant Pipelined RISC-V Processor with Instruction Cache
Wesley Grignani, Douglas Santos, Douglas Melo, Frédéric Wrobel and Luigi Dilillo
17:20
Runtime Pattern Identification and Ranked Fault Narrowing in SBST for RISC-V Processors
Ashwin Santhosh, Endri Kaja, Jad Al Halabi, Artur Jutman, Maksim Jenihhin and Wolfgang Ecker
17:40
SafeTCLS: Fast Error Recovery for a RISC-V Triple-Core Lockstep Realization
Ahlame El Afghani, Sergi Alcaide, Juan Carlos Rodríguez and Jaume Abella
17:50
Shifted-Scheduling Interleaved Multi-Threading for Hard-Fault Detection in a RISC-V Microprocessor
Andrea Marcelli, Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli and Mauro Olivieri
18:00
CFI Checking by Collaboration of Processor Compiler and its RTL Implementation
Sara Azizi, Tara Sarpoolaki, Bahareh Einollahi, Rayhaneh Einollahi, Mahdis Mirzaei, Saeed Safari and Zain Navabi
18:10
Welcome Reception
09:00
10:00
11:00
12:00
13:00
14:00
15:00
16:00
17:00
00:00
09:00
09:00 -
10:00
Keynote
Keynote by Yervant Zorian
10:00
Coffee Break and Poster Session
10:00 -
11:00
Poster
Session
Formal-Aided Reliability Assessment for Systolic Array-Based DNN Accelerators
Vu Dang Nguyen Trinh, Otmane Ait Mohamed, Fakhreddine Ghaffari and Ayoub Fellouh
RERI-Compliant RAS in Multilevel EDAC-Protected Cache Memories: The ENGAGE-V Framework
Nicasio Canino, Giovanni Mazzini, Daniele Rossi and Sergio Saponara
TMR Hardening and Validation of a 28nm RISC-V Microcontroller CPU for Harsh Radiation Environments
Anvesh Nookala, Marco Andorno, Benoît Denkinger, Alessandro Caratellli, Kostas Kloukinas, Axel Jantsch and Jeffrey Prinzie
PUDIM: Aging-Aware Processing-Using-DRAM via Informed Row Mapping
Maxime Zingraff, Fernando Fernandes dos Santos, Marcello Traiola and Angeliki Kritikakou
On the Cost-Security Trade-Off in Combinational Hardware Trojan Detection
Enkele Rama and Matthias Korb
Robust RTN parameter extraction under strong pink noise and baseline drift: Comparison of deep learning and FHMM-based methods
Théo Lafond, Pascal Urard, Kai Wang, Owen Gauthier and Sebastien Haendler
11:00
Session 4: Hardware Security, Aging, and Reliability Analysis
11:00 -
12:20
Regular
Session
11:00
HMMKeySpy: Probabilistic Key Recovery from Sliding-Window RSA on RISC-V
Sadia Shamas, Stefano Di Carlo and Alessandro Savino
11:20
Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis
Gijs Burghoorn, Ileana Buhan and Lejla Batina
11:30
STA-based Single Event Transient Analysis under Static NBTI-Induced Aging Effects
Pelopidas Tsoumanis, Georgios-Ioannis Paliaroutis, Nikolaos Chatzivangelis, Nikolaos Zazatis, Konstantinos Varakliotis, Fabian Vargas, Marko Andjelkovic and Christos P. Sotiriou
11:50
Aging Aware Functionally Possible Pulses and Path Delay Faults
Irith Pomeranz
12:00
Data-Efficient Cross-Generation Adaptation for Microcontroller Performance Screening
Nicolò Bellarmino, Alessandro Vancini, Tobias Kilian and Riccardo Cantoro
12:20
Lunch
13:50
Panel
13:50 -
15:40
Special
Session
Chair: Gianluca Furano
More details will be released soon.
15:40
Coffee Break
16:00
JASPER: Special Session on Joint Reliability And Security Assessment of SPlit Computing for Edge Robustness
16:00 -
17:00
Special
Session
Enrico Magliano, Giuseppe Esposito, Amirhossein Shahdadian, Rama Mounika Kodamanchili, Juan David Guerrero Balaguera, Juan Esteban Rodriguez Condia, Annachiara Ruospo, Roberto Siciliano, Stefano Di Carlo, Maksim Jenihhin, Marco Levorato, Alessandro Savino, Matteo Sonza Reorda, Christian Herglotz, Michael Hübner, Mahdi Taheri
17:00
10:00
11:00
12:00
13:00
14:00
15:00
10:00
Session 5: Advanced Test Techniques
10:00 -
11:10
Regular
Session
10:00
On the Acceleration of Multiple Target Test Generation Using Extended Test Cubes
Tao Sawada, Toshinori Hosokawa, Masayoshi Yoshimura, Yusuke Matsunaga and Masayuki Arai
10:10
Design for Test Observability of an AMBA-AXI Network Interface for Reliable MPSoCs
Thiago Rausch, Wesley Grignani, Douglas Santos, Luigi Dilillo and Douglas Melo
10:30
A Low-Power AC-Modulated On-chip Kelvin BIST with Lightweight Classification for Package-to-Board Interconnect Fault Detection
Boli Yang, Cheng Quan, Shuai Wang, Kai Su, Shanshan Liu, Pedro Reviriego, Zhen Gao, Fabrizio Lombardi, Wei Zhang, Yong Wang and Xiaochen Tang
10:50
Exploiting Systolic Array Dataflow to Perform Functional Parallel Test & Diagnosis
Lila Ammoura and Alberto Bosio
11:10
Coffee Break and Poster Session
11:10 -
12:10
Poster
Session
SCEPA: Decoupling Signal Correlation Extraction and Probability Annotation for Probabilistic Reliability
Christos Georgakidis and Christos P. Sotiriou
An FPGA Platform for Evaluating RowHammer-based DRAM PUFs
Roberto Capoferri, Luca Breveglieri and Paolo Maistri
10-Mrad Total Ionizing Dose Response of 28-nm Bulk CMOS Transistors for Aerospace Electronics
Luca Gelmi, Gabriele Andreetta, Matteo Chiariello, Fabio D'Ottavi, Elia Arturo Vallicelli, Mattia Tambaro, Stefano Bonaldo, Serena Mattiazzo, Adriano Lai and Marcello De Matteis
A FiRO-Based TRNG for Resource-Constrained Applications: Schematic-Level Full-Custom Design and Validation
Ettore Noccetti, Francesca Bagnoli, Mattia Bernini, Andrea Ria, Daniele Rossi and Sergio Saponara
Automated Assembly-Level Mitigation of Transient Execution Attacks using Code Variants and Genetic Optimization
Elia Lazzeri, Gabriele Giordanelli, Gianluca Furano and Luca Cassano
The Reliability Cost of Partial SIHFT: Fault-Injection and Neutron-Beam Evaluation of RTailor
Tijmen T. Smit, Shao-Yu Huang, Yida Zhang, Carlo Cazzaniga, Kuan-Hsun Chen, Changhee Jung and Marco Ottavi
12:10
Special Session on The Case for Security Primitives on Flexible Electronics
12:10 -
13:10
Special
Session
13:10
Lunch
14:40
Session 6: Reliability of Emerginig Computing Technologies
14:40 -
15:20
Regular
Session
14:40
Optimizing Run-Time Assertions for Quantum Circuit Debugging: A Depth–Ancilla Tradeoff
Karl Aaron Rudkowski, Abhoy Kole and Rolf Drechsler
15:00
Structure-Aware and Multi-Objective Test Generation for Digital Computing-in Memories with MAC Function
Wei-Hung Lin, Yu-Guang Chen, Ya-Chun Chang, Jin-Fu Li, Chun-Lung Hsu and Shih-Hsu Huang
15:10
Selective Hardening of Digital Spiking Neuromorphic Systems
Suman Kumar, Sarah Johari, Abhishek Kumar Mishra, Anup Das and Nagarajan Kandasamy
15:20
Closing & Awards