Keynotes

Dr. Martin Keim, Siemens EDA

A DFT Guide to Kill Your 3D Product and Ruin Your Company

Multi-die products, and in particular 3D products, will have a significant impact on how Design-For-Test (DFT) needs to be implemented, executed, and monitored throughout the life cycle of the product. There are many pitfalls associated with incorrect and incomplete DFT that will result in high test costs in both die area and test time, yield loss, or high shipped DPPM rates. None of this is desirable. On the other hand, DFT done right will add value to the product and the company. We will follow DFT as it evolves from classical “2D” designs into value-added solutions addressing the challenges of huge, multi-die products. We will touch on so-called “Known-Good Die,” test and repair of the multi-chip assembly, related test standards like IEEE 1838 and P1838a, IEEE P3405, IEEE 1687, and interfaces like PCIe, USB, and UCIe, among others. Addressing the increased test quality requirements while at the same time keeping the cost of test in check is the underlying theme throughout. In the end, we hope you will understand that for multi-die, 3D products, DFT can no longer be an afterthought but needs to become an upfront planned part of the entire 3D ecosystem.

Biography

Dr. Martin Keim joined the Tessent product group of Mentor Graphics in 2001, now part of Siemens EDA, where he is Senior Engineering Director responsible for Memory Testing, Built-In Self-Test Diagnosis, IJTAG, as well as multi-die testing. Dr. Keim is a past member of the IEEE 1687-2014 working group, past secretary of IEEE P1687.1, an active member of the IEEE P3405 and P1838a working groups, general chair of the current P1687 Refresh working group, and secretary of IEEE’s Test Technology Standards Committee.