DFT

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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Overview of the conference

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies, RISC-V architectures and AI-based solutions. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, availability, and security that are affected by defects during manufacturing and by faults during system operation are of interest.


Last Edition Conference Pictures

News and Dates

Latest Update

  • DFTS 2025 was a great edition, see you next year in Rome.
  • Special issue 2025 confirmed, extended versions can be submitted to MICPRO. See the dedicated page.

Regular Papers

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Call for papers

Join us for the DFT Annual Symposium, a premier platform for sharing insights on defect and fault tolerance in VLSI and nanotechnology systems, including emerging technologies, RISC-V architectures, and AI solutions. This unique event bridges cutting-edge academic research with valuable industrial data, fostering advancements in design, manufacturing, testing, reliability, availability, and security. We invite submissions on a wide range of topics related to defects and faults, and we look forward to your contributions.

PDF Version

  1. 1. Yield Analysis and Modeling
    Advanced yield models, defect/fault analysis, statistical modeling, and critical area analysis.
  2. 2. Testing Techniques
    Innovative testing methodologies for digital, analog, and mixed signal circuits, including built-in self-test, delay fault testing, online test and 2.5D/3D circuits.
  3. 3. Design For Testability
    DFT for modern ICs, including FPGAs, SoCs, NoCs, GPUs, ASICs, low-power designs, and RISC-V designs.
  4. 4. Error Detection, Correction, and Recovery
    Robust error handling strategies, including error-control coding, fault masking, and recovery schemes, using hardware/software techniques and architectural approaches.
  5. 5. Dependability Analysis and Validation
    Rigorous evaluation of system dependability, employing fault injection, cross-layer reliability analysis, and AI/ML-based methods.
  6. 6. Repair, Restructuring and Reconfiguration
    Dynamic adaptation techniques for fault tolerance and resilience, including self-healing reconfigurable circuits, and on-line repair.
  7. 7. Defect and Fault Tolerance
    Design of reliable systems in the presence of defects and faults, design space exploration for dependable systems, in critical applications and addressing transient/soft faults.
  8. 8. Aging and Radiation effects
    Radiation effects, radiation-induced errors in nano-technologies, modeling radiation environments, development of novel radiation test and simulation techniques and developing radiation hardened designs.
  9. 9. Aging and Lifetime Reliability
    Understanding aging mechanisms, designing for long-term reliability, and managing thermal and variability challenges.
  10. 10. Emerging Technologies
    Error management strategies for quantum computing, memristive devices, spintronics, microfluidics, and approximate computing.
  11. 11. RISC-V
    Use of open ISAs in dependable and security applications.
  12. 12. Design for Security
    Protecting ICs against fault attacks, hardware trojans, and other security threats, the interplay between security, reliability, and trust.
  13. 13. Dependable Applications and Case Studies
    Real world applications of dependability techniques in 2.5D/3D ICs, IoT, automotive, aerospace, autonomous systems, and AI systems.
  14. 14. Sustainability and Green EEE
    Highlight the need for energy-efficient and environmentally friendly EEE designs, including low-power design techniques and green manufacturing processes.

Organizing Committee

General Co-Chairs Marco Ottavi University of Rome Tor Vergata, Italy and University of Twente, The Netherlands m.ottavi@utwente.nl
Silvia Moranti European Space Agency ESTEC, The Netherlands silvia.moranti@esa.int
Program Co-Chairs Shanshan Liu University of Electronic Science and Technology of China, China ssliu@uestc.edu.cn
Petr Fišer Czech Technical University in Prague, Czech Republic petr.fiser@fit.cvut.cz
Finance Chair Gianluca Furano European Space Agency ESTEC, The Netherlands gianluca.furano@esa.int
Special Session Co-Chairs Bruno Forlin University of Twente, The Netherlands b.endresforlin@utwente.nl
Livia Manovi University of Bologna, Italy livia.manovi@unibo.it
Publicity and Web Chair Tijmen Smit University of Twente, The Netherlands t.t.smit@utwente.nl

Technical Sponsors