Special Issue

Authors are invited to submit a manuscript to the special section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. Relevant topics of interest to this special section include (but are not limited to) reliability and dependability-aware analysis and design methodologies:

1. Yield Analysis and Modeling:
   Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
2. Testing Techniques:
   Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.
3. Design for Testability in IC Design:
   FPGA, SoC, NoC, ASIC, low power design and microprocessors.
4. Error Detection, Correction, and Recovery:
   Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; HW/SW techniques; architectural and system-level techniques.
5. Dependability Analysis and Validation:
   Fault injection techniques and frameworks; dependability and characterization, cross-layer reliability analysis, dependability analysis for AI.
6. Repair, Restructuring and Reconfiguration:
   Repairable logic; reconfigurable circuit design; DFT for online operation; self-healing; reliable FPGA systems.
7. Radiation effects:
   SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.
8. Defect and Fault Tolerance:
   Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults.
9. Aging and Lifetime Reliability:
   Aging characterization and modeling; design and runtime reliability, thermal, and variability management and recovery.
10. Dependable Applications and Case Studies:
    Methodologies and case studies for IoTs, automotive, railway, avionics and space, autonomous systems, industrial control, failsafe systems, dependable AI, etc.
11. Emerging Technologies:
    Techniques for 2.5D/3D ICs, quantum computing architectures, memristors, spintronics, microfluidics, approximate computing, etc.
12. Design for Security:
    Fault attacks, fault tolerance-based countermeasures, scan-based attacks and countermeasures, hardware trojans, system obfuscation and logic locking, secure AI, security vs. reliability, interaction between VLSI test, trust, and reliability.

Submitted papers must include new significant research-based technical contributions in the scope of the journal. Papers under review elsewhere are not acceptable for submission. Extended versions of published conference papers (to be included as part of the submission together with a summary of differences) are welcome, but there must have at least 30% new impacting technical/scientific material in the submitted journal version and there should be less than 50% verbatim similarity level as reported by a tool (such as CrossRef).

Important dates

Manuscript submission information

The submission website for this journal is located at: https://www.editorialmanager.com/micrel/default.aspx
To ensure that all manuscripts are correctly identified for inclusion into the special issue you are editing, it is important that authors select the name of the special issue when they upload their manuscripts: "VSI: DFTS_2022". Guidelines for preparing your manuscript may be found at: https://www.elsevier.com/journals/microelectronics-reliability/0026-2714/guide-for-authors
More information about the special issue can be found at: https://www.sciencedirect.com/journal/microelectronics-reliability/about/call-for-papers