Final Program

October 19th

08:00 - 08:45: Registration + Breakfast
08:45 - 09:00: Opening Session
09:00 - 10:00: Keynote 1: Sriram Sankar
Session Chair: Prashant Joshi
Coffee break
10:15 - 11:30: Regular Session 1: Reliability analysis
Session Chair: Paolo Bernardi
  1. Image Degradation due to Interacting Adjacent Hot Pixels
    2. Glenn Chapman, Klinsmann Joel J. Coelho Silva Meneses, Israel Koren and Zahava Koren
  2. Understanding time-varying vulnerability for efficient GPU program hardening
    Hao Qiu, Semiu Olowogemo, Bor-Tyng Lin, William Robinson and Daniel Limbrick
  3. SET Hardened Derivatives of QDI Buffer Template
    Zaheer Tabassam and Andreas Steininger
11:30 - 14:30: Visit to the Texas Advanced Computing Center + Lunch
14:30 - 15:45: Special Session 1: RISC-V based architectures for safety-critical applications
Session Chair: Amlan Ghosh
  1. Toward the hardening of real-time operating systems
    Alberto Bosio, Stefano Di Carlo, Maurizio Rebaudengo and Alessandro Savino
  2. Is RISC-V ready for Space? A Security Perspective
    Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi and Marco Ottavi
  3. Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip
    4. Douglas Santos, Andre Mattos, Lucas Luza, Carlo Cazzaniga, Maria Kastriotou, Douglas Melo and Luigi Dilillo
Coffee break
16:00 - 17:15: Regular Session 2: Security: attacks and countermeasures
Session Chair: Majed Valad Beigi
  1. CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level
    Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki and Toshinori Hosokawa
  2. Preventing Soft Errors and Hardware Trojans in RISC-V Cores
    Edian Annink, Gerard Rauwerda, Edwin Hakkennes, Alessandra Menicucci, Stefano Di Mascio, Gianluca Furano and Marco Ottavi
  3. Evaluation of Hiding-based Countermeasures against Deep Learning Side Channel Attacks with Pre-trained Networks
    4. Konstantinos Nomikos, Athanasios Papadimitriou, Mihalis Psarakis, Aggelos Pikrakis and Vincent Beroulle
Free time

October 20th

08:30 - 09:30: Registration + Breakfast
09:30 - 10:30: Keynote 2: Sankaran Menon
Session Chair: Luigi Dilillo
Coffee break
10:45 - 12:00: Regular Session 3: Microprocessors
Session Chair: Israel Koren
  1. Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded Processor
    Corrado De Sio, Sarah Azimi, Luca Sterpone and David Merodio Codinachs
  2. INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling
    3. Panagiota Nikolaou, Yiannakis Sazeides and Maria K. Michael
12:00 - 13:15: Special Session 2: Hardware Architectures for Post-quantum cryptography: Arithmetic, Efficiency, and Security
Session Chair: Jiafeng Xie
  1. HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU
    Pengzhou He, Hazhen Tu, Ayesha Khalid, M'Aire O'Neill and Jiafeng Xie
  2. Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography
    Antian Wang, Weihang Tan, Yingjie Lao and Keshab K. Parhi
  3. Loop Abort Fault Attacks on Supersingular Isogeny based Key Exchange (SIKE)
    4. Piyush Beegala, Debapriya Basu Roy, Prasanna Ravi Ravi, Shivam Bhasin, Anupam Chattopadhyay and Debdeep Mukhopadhyay
Lunch break
14:30 - 15:45: Regular Session 4: All the facets of testing
Session Chair: Glenn Chapman
  1. Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level
    Francesco Angione, Paolo Bernardi, Gabriele Filipponi, Claudia Tempesta, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre and Roberto Ugioili
  2. Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing
    Praise Farayola, Isaac Bruce, Shravan Chaganti, Abalhassan Sheikh, Srivaths Ravi and Degang Chen
  3. Storage-Based Logic Built-In Self-Test with Variable-Length Test Data
    4. Irith Pomeranz
15:45 - 17:00: Coffee break + Poster Session
  1. Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies
    Semiu Olowogemo, Hao Qiu, Bor-Tyng Lin, William Robinson and Daniel Limbrick
  2. Aging Effects On Clock Gated Memory Phase Paths
    Amlan Ghosh, Saroj Satapathy, Prashant Joshi and Jaydeep Kulkarni
  3. Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent Faults
    Raghda El Shehaby and Andreas Steininger
  4. MetaFS: Model-driven Fault Simulation Framework
    Endri Kaja, Nicolas Gerlin, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz and Wolfgang Ecker
  5. X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective
    Nasr-Eddine Ouldei Tebina, Nacer-Eddine Zergainoh and Paolo Maistri
  6. Operational Age Estimation of ICs using Gaussian Process Regression
    Anmol Singh Narwariya, Pabitra Das, Saqib Khursheed and Amit Acharyya
  7. Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor Systems
    Masoomeh Karami, Hashem Haghbayan, Antonio Miele, Masoumeh Ebrahimi and Juha Plosila
17:30 - : Social Event: Dinner Cruise

October 21st

08:30 - 09:30: Registration + Breakfast
09:30 - 10:30: Keynote 3: Carlos Tokunaga
Session Chair: Luca Cassano
Coffee break
10:45 - 12:00: Regular Session 5: Deep learning hardening
Session Chair: Shanshan Liu
  1. Improving DNN Fault Tolerance in Semantic Segmentation Applications
    Stéphane Burel, Adrian Evans and Lorena Anghel
  2. Selective Hardening of CNNs based on Layer Vulnerability Estimation
    Cristiana Bolchini, Luca Cassano, Antonio Miele and Alessandro Nazzari
  3. Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages
    4. Jianan Wen, Andrea Baroni, Eduardo Perez, Markus Ulbricht, Christian Wenger and Milos Krstic
12:00 - 13:15: Regular Session 6: Radiation effects
Session Chair: Luigi Dilillo
  1. Evaluation of the Effects of SEUs on Configuration Memories in FPGA Implemented LDPC Decoders
    Gao Zhen, Cheng Yinghao and Pedro Reviriego
  2. RADPlace-MS: An Improved Timing-Driven Placer and Optimiser for ASICs Radiation Hardening
    Christos Georgakidis, Stavros Simoglou, Christos Sotiriou
  3. A Polarity-Driven Radiation-Hardened Latch design for Single Event Upset Tolerance
    4. Shanshan Liu, Jing Guo, Xiaochen Tang, Pedro Revriiego and Fabrizio Lombardi
Lunch break
14:30 - 14:45: Best papers announcement
14:45 - 15:00: Closing remarks