Special Section on Emerging Topics in Computing
The IEEE Transactions on Emerging Topics in Computing seeks original manuscripts for a Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems scheduled to appear in the December issue of 2016.
The topics of interest for these special sections include, but are not limited to:
- Yield Analysis and Modeling
Defect/Fault analysis and models; statistical yield modelling; critical area and metrics. - Testing Techniques
Built-in self-test; delay fault modelling and diagnosis; testing for analogue and mixed circuits; signal and clock integrity. - Design For Testability in IC Design
FPGA, SoC, NoC, ASIC, microprocessors. - Error Detection, Correction, and Recovery
Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques. - Dependability Analysis and Validation
Fault injection techniques and environments; dependability characterization. - Repair, Restructuring and Reconfiguration
Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing. - Defect and Fault Tolerance
Reliable circuit/system synthesis; radiation hardened and/or tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors; Performance, power, reliability tradeoffs. - Totally Fail-Safe Design for Critical Applications
Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks. - Emerging Technologies
Techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly. - Hardware Security
Fault attacks, fault tolerance-based counter-measures, Scan-based attacks and counter-measures, hardware trojans, security versus reliability tradeoffs, interaction between VLSI test, trust, and reliability.
Submitted articles must describe original research which is not published nor currently under review by other journals or conferences. Extended conference papers should contain at least 40% new material and will pass through the normal review process. As an author, you are responsible for understanding and adhering to our submission guidelines. You can access them at the IEEE Computer Society web site, www.computer.org. Please thoroughly read these before submitting your manuscript. TETC is the newest Transactions of the IEEE Computer Society with hybrid open access publishing model. At the proper time, authors are invited to submit manuscripts through TETC submission site (https://mc.manuscriptcentral.com/tetc-cs).
Important dates
| Submission | December 1, 2015 |
| Reviews Completed | March 1, 2016 |
| Major Revision due (if needed) | April 1, 2016 |
| Reviews of revisions | May 1, 2016 |
| Minor Revision due (if needed) | June 1, 2016 |
| Final notification of acceptance/rejection | August 1, 2016 |
| Publication material for final manuscripts due | September 1, 2016 |
| Special Section publication | issue December 2016 |
Guest editors
- Omer Khan (University of Connecticut)
- Maria K. Michael (University of Cyprus)
- Salvatore Pontarelli (CNIT - Italian Inter-University Consortium of Telecommunications, Italy)
Flyer
Downloadable Call for Papers pdf.